This invention is in the field of data communications, and is more specifically directed to the management of data communications in a digital system.
Digital data communications has become an ever-increasing function of modern digital systems, as a result of the vast improvements in communications technology over recent years. Data communications functionality can now be realized in virtually every digital system, ranging from miniature hand-held devices such as cameras and digital audio players, to large-scale computer systems, servers, and web hosting facilities. The manner in which such communications is carried out varies, of course, with the particular communications technology being used. Computer systems connected into a local area network (LAN) include Ethernet adapters for wired network communications, or wireless adapters such as those operating according to the well-known IEEE 802.11a/b/g/n standards. Cable or Digital Subscriber Line (DSL) modems provide communications between computers and networks, on one hand, and telephone or cable communications service providers, on the other hand, according to the applicable standard. Digital set-top boxes provide digital communications between home entertainment systems and cable or satellite television and communications service providers. Wireless telephone service providers operate base stations deployed throughout cities and rural areas, each of which manage and support communications with wireless telephone handsets and network devices (e.g., broadband wireless network cards for laptop computers).
Much of modern digital communications communicate digital data between nodes or elements in a network in the form of “packets”. In this approach, the payload data are subdivided into discrete blocks of data (“packets”) which are individually routed over the data network, typically along with other packets being communicated between other source and destination nodes. Packet communications may be point-to-point, in which the source and destination nodes are in direct communication with one another, or carried out in a packet switching environment, in which the packets in a given message or communication are communicated through intermediate nodes, and often over different logical data streams. At the intermediate nodes, in this context, each packet is typically queued and buffered at each network node along the overall data path between source and destination. A wide range of communications services utilize packet-based communications, including Ethernet, Internet Protocol (IP), frame relay communications, Asynchronous Transfer Mode (ATM), and the like.
Fundamentally, packets include a descriptor and an associated data element. The descriptor includes information such as the current location of the data element in memory, the size of the data element, and other identifying and control information. A communications message consisting of multiple packets is conventionally managed by way of a “linked list”, in which the descriptor for a given packet includes a memory address pointing to the location of the descriptor of the next packet in sequence within the message. The communications device or system transmitting or receiving the message thus processes a packet, with its descriptor and data element, and then next processes the packet to which the descriptor of the previous packet points.
FIG. 1 illustrates, in block form, the arrangement of a network adapter, in a digital system, as it carries out the communication of a multiple-packet message using a linked list. In the arrangement of FIG. 1, this network adapter includes Ethernet driver 2, which manages the communication of data to and from an external Ethernet network in this example. Ethernet driver 2 manages this communication by way of a linked list of data packets. For the example of transmission by Ethernet driver 2, each data packet will be transmitted as the payload of its own communications packet, along with the appropriate header information for the particular network protocol. The complete message is thus transmitted as a sequence of individual packets, which may be interspersed with packets from other messages. The destination of the message will then resequence the packets into the overall message.
In the arrangement of FIG. 1, physical memory resources 6a, 6b store data packets 8 and their corresponding descriptors 4. In this network adapter, as is typical for conventional network adapters, memory resource 6a is realized by “on-chip” memory that is local to the central processing unit and other programmable logic carrying out the function of the network adapter, while memory resource 6b is realized as “off-chip” memory external to that programmable logic. In each case, memory resources 6a, 6b are typically random access memory. The external “off-chip” memory resource 6b is provided to reduce the cost of the local programmable logic of the network adapter, and can provide a relatively large memory capacity to the adapter. However, accesses to external memory resource 6b are necessarily slower than accesses to on-chip memory resource 6a, due to differences in the access times of the memories themselves, as well as the control overhead required to access external memory.
In this conventional arrangement of a network adapter shown in FIG. 1, two functions operate on communications packets stored in memory resources 6a, 6b. As mentioned above, one of these functions is Ethernet driver 2, which manages the transmission of data packets stored in memory resources 6a, 6b to the network, and which manages the receipt of data packets from the network and their storage in memory resources 6a, 6b. In addition, this conventional network adapter is also in communication with host application 10, which generates and places data packets that are to be transmitted over the network into memory resources 6a, 6b, and which retrieves data packets received over the network from memory resources 6a, 6b for further processing according to the particular application and host system.
In conventional packet-based network communications, management and processing of data packets 8 in the form of a “linked list”, representing a queue that is maintained at a network processing point, has proven to be useful. This concept is applied at the network processing point, such as within a network adapter, in converting an incoming stream of data packets (whether being transmitted or received over the network) into a linked list of descriptors, and buffers associated with those descriptors. FIG. 1 illustrates how a typical linked list of data packets 8 is maintained in such a conventional network adapter. Each data packet 8 has a corresponding descriptor 4 that is also stored somewhere in memory resources 6a, 6b. The size of a given descriptor 4 can vary from a few bytes to several kilobytes, depending on the protocol and the particular type of packet, with packet descriptors of multiple sizes are often simultaneously managed within a conventional network adapter. In the arrangement of FIG. 1, as is typical, each descriptor 4 includes information regarding its associated data packet 8, including its size and memory location. The applicable network protocol standard typically defines the structure and contents of descriptors 4, as known in the art.
To implement the queue as a linked list, each descriptor 4 includes a “next” pointer, which is the memory location of the descriptor 4 that is next in the transmission (or receipt) queue. In the example of FIG. 1, descriptor 4(n) includes a next pointer that is storing the memory address, in memory resource 6a, of descriptor 4(n+1). Similarly, descriptor 4(n+1) includes a next pointer storing the memory address of descriptor 4(n+2), and descriptor 4(n+2) includes a next pointer storing the memory address of descriptor 4(n+3). In this manner, the linked list is established by each descriptor 4 identifying the next descriptor 4 in the sequence. As evident from FIG. 1 and as conventional in the art, each descriptor 4(n) through 4(n+3) also stores the memory address of its corresponding data packet 8(n) through 8(n+3), respectively, as well as other information regarding that data packet 8. The data packets 8 need not reside in the same memory resource 6a, 6b as its corresponding descriptor 4. For example, data packet 8(n+1) is stored in external memory resource 6b, while its associated descriptor 4(n+1) is stored in on-chip memory resource 6a. 
It has been observed, in connection with this invention, that the conventional arrangement of FIG. 1 limits performance in several ways. As discussed above, access to those descriptors 4 that are stored in external memory resource 6b can be relatively slow as compared with access to descriptors 4 in on-chip memory resource 6a. But because the memory requirements of descriptors 4 necessitate such storage in both on-chip and off-chip memory, the overall performance of the network adapter in queue management (e.g., writing or retrieving the contents of the next pointers as a packet is added to the queue) can suffer. In addition, the arrangement of FIG. 1 is vulnerable to data coherency problems, given the separate access to memory resources 6a, 6b by host application 10 and Ethernet driver 2, each of which is managing one or more transmission or receipt queues, independently from the other.
In the conventional arrangement described above relative to FIG. 1, a list or “pool” of free descriptors is maintained, to permit the network adapter to define new packets (i.e., packet descriptor and its associated data packet) for data to be transmitted or newly received data. In this example, host application 10 and Ethernet driver 2 each have access to this free descriptor pool, which is essentially a linked list queue of these descriptors. As noted above, on-chip memory resources 6a are typically not of adequate size to store all of the packet descriptors 4 that are available for use; indeed, it is contemplated that external memory resource 6b will commonly store a significant number of packet descriptors 4. As a result, selection of a free descriptor upon receipt or transmission of a new packet will often select a free descriptor in external memory resource 6b rather than from on-chip memory resource 6a, which necessarily involves a performance penalty due to the increased latency of accesses to external memory.